This invention relates generally to digital circuits and specifically to a clock signal having reduced measurable electromagnetic interference emissions.
Electronic devices generate electromagnetic interference (EMI) when operating. The EMI generated by one electronic device may adversely affect the operation of another electronic device. In order to minimize adverse effects of EMI upon other electronic devices, the United States and other countries have adopted standards which limit the amount of energy an electronic device may radiate at any given frequency.
Electronic devices having digital circuitry typically require a clock signal of some frequency for operation. In many such devices, long traces or wires are used to route the clock signal to various integrated circuit (IC) components. These long wires or traces act as antennas which, in turn, radiate energy at the clock signal frequency and its harmonics. Since antennas radiate more efficiently as wavelength becomes smaller with respect to antenna length, the amount of energy so radiated increases as the clock frequency increases. Consequently, in sophisticated electronic devices such as, for instance, personal computers, where clock frequencies are approaching gigahertz speeds, EMI is increasingly problematic and often prevents electronic devices from being sold to the public because of failure to meet FCC EMI limits.
FIG. 1 shows a spectral plot of energy versus frequency for an ideal clock of frequency fCLK. All of the EMI energy is concentrated at the clock frequency fCLK (energy at harmonics of the clock frequency are not shown for simplicity). Since EMI energy exceeds FCC limits at the clock frequency for this clock, a device included with this much radiated energy would not meet FCC regulations. A well known technique to reduce the peak EMI energy at the clock frequency (and its harmonics) is to use frequency hopping spread spectrum techniques to spread the energy across the frequency spectrum, as shown in FIG. 2. Spectrum spreading is commonly used in radio frequency communication to facilitate high-resolution ranging, multiple access, jamming resistant waveforms, and energy density reduction.
Conventional techniques for generating a spread spectrum clock signal typically involve varying the frequency of the clock signal in a periodic manner between two predetermined frequencies. For instance, in U.S. Pat. No. 5,610,955, a phased-locked loop (PLL) circuit receiving as input a signal at a reference frequency is used with variable feedback to generate a spread spectrum clock. A first divider circuit coupled to the PLL input divides the reference frequency by a first variable integer M, and a second divider circuit coupled to the PLL output divides the output frequency by a second variable integer N, where the first and second integers M and N are periodically varied by a control circuit, so as to cause the frequency of the output signal to vary precisely between two predetermined frequencies. U.S. Pat. No. 5,631,920 discloses a slightly different approach, whereby the frequency of a clock signal is modulated according to a periodic waveform having a predetermined period and a predetermined frequency profile.
Although conventional techniques for generating a spread spectrum clock in order to reduce EMI spikes at the harmonic frequencies are often sufficient, ever increasing clock speeds require continually improving EMI spreading techniques. Further, such conventional techniques are not suitable for all systems. For example, the time-varying clock frequency techniques discussed above may not be suitable for systems which use PLLs, since PLLs require certain bandwidth to track the clock.
A direct sequence spread spectrum clock circuit is disclosed which reduces EMI of an electronic system. In accordance with the present invention, a clock signal desired to be distributed to various components of the electronic system is combined with a noise signal to generate a spread spectrum clock signal. The spread spectrum clock signal and an associated transmitted reference signal are distributed to selected components of the system using two-channel communication links or by using synchronized pseudo-random number generators in each component. A receiving circuit within each of the selected components recovers the original clock signal from the spread spectrum clock signal and the reference signal. In some embodiments, synchronized code generators housed within transmitting and receiving components are employed.
The noise signal, being either random or pseudo-random, causes the resulting spread spectrum clock signal to be non-periodic. As a result, energy radiated by the spread spectrum clock signal is spread over a wide frequency band. Applicants have found that the non-periodic nature of the direct sequence spread spectrum clock signal waveform results in improved EMI reduction, as compared to conventional EMI reduction techniques discussed above.
In one embodiment, a clock signal is combined with the noise signal in an exclusive-OR logic gate to generate a spread spectrum clock signal which, in turn, is transmitted to receiving components using a first channel. The noise signal is transmitted as the reference signal using a second channel. The two channel signals are combined in an exclusive-OR gate of one or more receiving circuits to recover the clock signal.
In another embodiment, transmission of the clock signal is alternated between two channels in accordance with the logic state of the noise signal. Here, the two channel signals are combined in an OR logic gate of each receiving circuit to recover the clock signal. In yet another embodiment, transmission of the clock signal is alternated between the two channels according to the logic state of the noise signal, and transmission of a reference voltage signal is alternated between the two channels in a complementary manner. Here, the two channel signals are combined in a comparator circuit within each receiving circuit to recover the clock signal.
In still another embodiment, identical pseudo-random number generators are housed in the clock generator as well as in each receiving device. After being synchronized, the pseudo-random signal and the clock are combined in an exclusive-OR logic gate. The resulting spread spectrum clock signal is distributed on a single channel.